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INTEGRATED CIRCUITS
DATA SHEET
TEA1062; TEA1062A Low voltage transmission circuits with dialler interface
Product specification Supersedes data of 1996 Dec 04 File under Integrated Circuits, IC03 1997 Sep 03
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
FEATURES * Low DC line voltage; operates down to 1.6 V (excluding polarity guard) * Voltage regulator with adjustable static resistance * Provides a supply for external circuits * Symmetrical high-impedance inputs (64 k) for dynamic, magnetic or piezoelectric microphones * Asymmetrical high-impedance input (32 k) for electret microphones * DTMF signal input with confidence tone * Mute input for pulse or DTMF dialling - TEA1062: active HIGH (MUTE) - TEA1062A: active LOW (MUTE) * Receiving amplifier for dynamic, magnetic or piezoelectric earpieces * Large gain setting ranges on microphone and earpiece amplifiers * Line loss compensation (line current dependent) for microphone and earpiece amplifiers * Gain control curve adaptable to exchange supply * DC line voltage adjustment facility. QUICK REFERENCE DATA SYMBOL VLN Iline line voltage operating line current normal operation with reduced performance ICC VCC internal supply current supply voltage for peripherals TEA1062 TEA1062A Gv voltage gain microphone amplifier receiving amplifier Tamb Gv Vexch Rexch 1997 Sep 03 operating ambient temperature Line loss compensation gain control exchange supply voltage exchange feeding bridge resistance 2 VCC = 2.8 V Iline = 15 mA PARAMETER CONDITIONS Iline = 15 mA
TEA1062; TEA1062A
GENERAL DESCRIPTION The TEA1062 and TEA1062A are integrated circuits that perform all speech and line interface functions required in fully electronic telephone sets. They perform electronic switching between dialling and speech. The ICs operate at line voltage down to 1.6 V DC (with reduced performance) to facilitate the use of more telephone sets connected in parallel. All statements and values refer to all versions unless otherwise specified.
MIN. 3.55 11 1 -
TYP. 4.0 - - 0.9 2.7 3.4 2.7 3.4 - - -
MAX. 4.25 140 11 1.35 - - - - 52 31 +75 - 60 1
UNIT V mA mA mA V V V V dB dB C
Ip = 1.2 mA; MUTE = HIGH 2.2 Ip = 0 mA; MUTE = HIGH Ip = 0 mA; MUTE = LOW - - 44 20 -25 - 36 0.4 Ip = 1.2 mA; MUTE = LOW 2.2
5.8 - -
dB V k
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TEA1062 TEA1062M1 TEA1062A TEA1062AM1 TEA1062T TEA1062AT BLOCK DIAGRAM DIP16 DIP16 DIP16 DIP16 SO16 SO16 DESCRIPTION
TEA1062; TEA1062A
VERSION SOT38-1 SOT38-4 or SOT38-9 SOT38-1 SOT38-4 or SOT38-9 SOT109-1 SOT109-1
plastic dual in-line package; 16 leads (300 mil) plastic dual in-line package; 16 leads (300 mil) plastic dual in-line package; 16 leads (300 mil) plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic small outline package; 16 leads; body width 3.9 mm
VCC
handbook, full pagewidth
LN 1 5 4 GAR QR
13 IR 10
TEA1062A
MIC MIC
7 2 6 GAS1
DTMF
(1)
11 12
dB
3
GAS2
MUTE
SUPPLY AND REFERENCE CONTROL CURRENT LOW VOLTAGE CIRCUIT
CURRENT REFERENCE 9 VEE 14 15 8 STAB 16 SLPE
MBA359 - 1
REG AGC
(1) Pin 12 is active HIGH (MUTE) for TEA1062.
Fig.1 Block diagram for TEA1062A.
1997 Sep 03
3
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
PINNING SYMBOL LN GAS1 GAS2 QR GAR MIC- MIC+ STAB VEE IR DTMF MUTE VCC REG AGC SLPE Note 1. Pin 12 is active HIGH (MUTE) for TEA1062. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION positive line terminal gain adjustment; transmitting amplifier gain adjustment; transmitting amplifier non-inverting output; receiving amplifier gain adjustment; receiving amplifier inverting microphone input non-inverting microphone input current stabilizer negative line terminal receiving amplifier input dual-tone multi-frequency input mute input (see note 1) positive supply decoupling voltage regulator decoupling automatic gain control input slope (DC resistance) adjustment
handbook, halfpage
TEA1062; TEA1062A
LN GAS1 GAS2 QR GAR MIC MIC STAB
1 2 3 4 TEA1062A 5 6 7 8
MBA354 - 1
16 SLPE 15 AGC 14 REG 13 VCC 12 MUTE 11 DTMF 10 IR 9 VEE
Fig.2 Pin configuration for TEA1062A.
1997 Sep 03
4
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
FUNCTIONAL DESCRIPTION Supplies VCC, LN, SLPE, REG and STAB Power for the IC and its peripheral circuits is usually obtained from the telephone line. The supply voltage is derived from the line via a dropping resistor and regulated by the IC. The supply voltage VCC may also be used to supply external circuits e.g. dialling and control circuits. Decoupling of the supply voltage is performed by a capacitor between VCC and VEE. The internal voltage regulator is decoupled by a capacitor between REG and VEE. The DC current flowing into the set is determined by the exchange supply voltage Vexch, the feeding bridge resistance Rexch and the DC resistance of the telephone line Rline. The circuit has an internal current stabilizer operating at a level determined by a 3.6 k resistor connected between STAB and VEE (see Fig.9). When the line current (Iline) is more than 0.5 mA greater than the sum of the IC supply current (ICC) and the current drawn by the peripheral circuitry connected to VCC (Ip) the excess current is shunted to VEE via LN. The regulated voltage on the line terminal (VLN) can be calculated as: VLN = Vref + ISLPE x R9 VLN = Vref + {(Iline - ICC - 0.5 x 10-3 A) - Ip} x R9 Vref is an internally generated temperature compensated reference voltage of 3.7 V and R9 is an external resistor connected between SLPE and VEE. In normal use the value of R9 would be 20 . Changing the value of R9 will also affect microphone gain, DTMF gain, gain control characteristics, sidetone level, maximum output swing on LN and the DC characteristics (especially at the lower voltages). Under normal conditions, when ISLPE >> ICC + 0.5 mA + Ip, the static behaviour of the circuit is that of a 3.7 V regulator diode with an internal resistance equal to that of R9. In the audio frequency range the dynamic impedance is largely determined by R1. Fig.3 shows the equivalent impedance of the circuit.
handbook, halfpage
TEA1062; TEA1062A
LN L eq Rp R1
V ref R9 20 V EE
REG
VCC
C3 4.7 F
C1 100 F
MBA454
Leq = C3 x R9 x Rp. Rp = 16.2 k.
Fig.3 Equivalent impedance circuit.
At line currents below 9 mA the internal reference voltage is automatically adjusted to a lower value (typically 1.6 V at 1 mA). This means that more sets can be operated in parallel with DC line voltages (excluding the polarity guard) down to an absolute minimum voltage of 1.6 V. At line currents below 9 mA the circuit has limited sending and receiving levels. The internal reference voltage can be adjusted by means of an external resistor (RVA). This resistor when connected between LN and REG will decrease the internal reference voltage and when connected between REG and SLPE will increase the internal reference voltage. Current (Ip) available from VCC for peripheral circuits depends on the external components used. Fig.10 shows this current for VCC > 2.2 V. If MUTE is LOW (TEA1062) or MUTE is HIGH (TEA1062A) when the receiving amplifier is driven, the available current is further reduced. Current availability can be increased by connecting the supply IC (TEA1081) in parallel with R1 as shown in Fig.19 and Fig.20, or by increasing the DC line voltage by means of an external resistor (RVA) connected between REG and SLPE (Fig.18).
1997 Sep 03
5
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
Microphone inputs MIC+ and MIC- and gain pins GAS1 and GAS2 The circuit has symmetrical microphone inputs. Its input impedance is 64 k (2 x 32 k) and its voltage gain is typically 52 dB (when R7 = 68 k, see Figures 14 and 15). Dynamic, magnetic, piezoelectric or electret (with built-in FET source followers) can be used. Microphone arrangements are illustrated in Fig.11. The gain of the microphone amplifier can be adjusted between 44 dB and 52 dB to suit the sensitivity of the transducer in use. The gain is proportional to the value of R7 which is connected between GAS1 and GAS2. Stability is ensured by two external capacitors, C6 connected between GAS1 and SLPE and C8 connected between GAS1 and VEE. The value of C6 is 100 pF but this may be increased to obtain a first-order low-pass filter. The value of C8 is 10 times the value of C6. The cut-off frequency corresponds to the time constant R7 x C6. Input MUTE (TEA1062) When MUTE is HIGH the DTMF input is enabled and the microphone and receiving amplifier inputs are inhibited. The reverse is true when MUTE is LOW or open-circuit. MUTE switching causes only negligible clicking on the line and earpiece output. If the number of parallel sets in use causes a drop in line current to below 6 mA the speech amplifiers remain active independent to the DC level applied to the MUTE input. Input MUTE (TEA1062A) When MUTE is LOW or open-circuit, the DTMF input is enabled and the microphone and receiving amplifier inputs are inhibited. The reverse is true when MUTE is HIGH. MUTE switching causes only negligible clicking on the line and earpiece output. If the number of parallel sets in use causes a drop in line current to below 6 mA the DTMF amplifier becomes active independent to the DC level applied to the MUTE input. Dual-tone multi-frequency input DTMF When the DTMF input is enabled dialling tones may be sent on to the line. The voltage gain from DTMF to LN is typically 25.5 dB (when R7 = 68 k) and varies with R7 in the same way as the microphone gain. The signalling tones can be heard in the earpiece at a low level (confidence tone).
TEA1062; TEA1062A
Receiving amplifier IR, QR and GAR The receiving amplifier has one input (IR) and a non-inverting output (QR). Earpiece arrangements are illustrated in Fig.12. The IR to QR gain is typically 31 dB (when R4 = 100 k). It can be adjusted between 20 and 31 dB to match the sensitivity of the transducer in use. The gain is set with the value of R4 which is connected between GAR and QR. The overall receive gain, between LN and QR, is calculated by subtracting the anti-sidetone network attenuation (32 dB) from the amplifier gain. Two external capacitors, C4 and C7, ensure stability. C4 is normally 100 pF and C7 is 10 times the value of C4. The value of C4 may be increased to obtain a first-order low-pass filter. The cut-off frequency will depend on the time constant R4 x C4. The output voltage of the receiving amplifier is specified for continuous-wave drive. The maximum output voltage will be higher under speech conditions where the peak to RMS ratio is higher. Automatic Gain Control input AGC Automatic line loss compensation is achieved by connecting a resistor (R6) between AGC and VEE. The automatic gain control varies the gain of the microphone amplifier and the receiving amplifier in accordance with the DC line current. The control range is 5.8 dB which corresponds to a line length of 5 km for a 0.5 mm diameter twisted-pair copper cable with a DC resistance of 176 /km and average attenuation of 1.2 dB/km). Resistor R6 should be chosen in accordance with the exchange supply voltage and its feeding bridge resistance (see Fig.13 and Table 1). The ratio of start and stop currents of the AGC curve is independent of the value of R6. If no automatic line-loss compensation is required the AGC pin may be left open-circuit. The amplifiers, in this condition, will give their maximum specified gain.
1997 Sep 03
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Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
Sidetone suppression The anti-sidetone network, R1//Zline, R2, R3, R8, R9 and Zbal, (see Fig.4) suppresses the transmitted signal in the earpiece. Maximum compensation is obtained when the following conditions are fulfilled: R8 x Z bal (1) R9 x R2 = R1 x R3 + ------------------------ R8 + Z bal Z line Z bal ------------------------ = ------------------------Z bal + R8 Z line + R1 (2) EXAMPLE
TEA1062; TEA1062A
The balance impedance Zbal at which the optimum suppression is present can be calculated by: Suppose Zline = 210 + (1265 //140 nF) representing a 5 km line of 0.5 mm diameter, copper, twisted-pair cable matched to 600 (176 /km; 38 nF/km). When k = 0.64 then R8 = 390 ; Zbal = 130 + (820 //220 nF). The anti-sidetone network for the TEA1060 family shown in Fig.4 attenuates the signal received from the line by 32 dB before it enters the receiving amplifier. The attenuation is almost constant over the whole audio-frequency range. Figure 5 shows a conventional Wheatstone bridge anti-sidetone circuit that can be used as an alternative. Both bridge types can be used with either resistive or complex set impedances. (More information on the balancing of anti-sidetone bridges can be obtained in our publication "Applications Handbook for Wired telecom systems, IC03b", order number 9397 750 00811.)
If fixed values are chosen for R1, R2, R3 and R9, then condition (1) will always be fulfilled when |R8//Zbal| << R3. To obtain optimum sidetone suppression, condition (2) has to be fulfilled which results in: R8 Z bal = ------- x Z line = k x Z line R1 R8 Where k is a scale factor; k = ------R1 The scale factor k, dependent on the value of R8, is chosen to meet the following criteria: * compatibility with a standard capacitor from the E6 or E12 range for Zbal * Zbal//R8 << R3 fulfilling condition (a) and thus ensuring correct anti-sidetone bridge operation * Zbal + R8 >> R9 to avoid influencing the transmit gain. In practise Zline varies considerably with the line type and length. The value chosen for Zbal should therefore be for an average line length thus giving optimum setting for short or long lines.
1997 Sep 03
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Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
LN
handbook, full pagewidth
Zline
R1
R2
VEE
im R3 R9 R8 SLPE Zbal
IR Rt
MSA500 - 1
Fig.4 Equivalent circuit of TEA1060 family anti-sidetone bridge.
book, full pagewidth
LN
R1 Zline
Zbal
VEE
im
IR Rt
R9
R8
RA
SLPE
MSA501 - 1
Fig.5 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.
1997 Sep 03
8
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VLN VLN(R) VLN(RM) Iline VI Ptot PARAMETER positive continuous line voltage repetitive line voltage during switch-on or line interruption repetitive peak line voltage for a 1 ms pulse per 5 s line current input voltage on all other pins total power dissipation TEA1062; TEA1062A TEA1062M1; TEA1062AM1 TEA1062T; TEA1062AT Tamb Tstg Tj Notes operating ambient temperature storage temperature junction temperature R9 = 20 ; R10 = 13 ; see Fig.18 R9 = 20 ; note 1 positive input voltage negative input voltage R9 = 20 ; note 2 CONDITIONS
TEA1062; TEA1062A
MIN. - - - - - - - - - -25 -40 - 12
MAX. 13.2 28 140 VCC + 0.7 -0.7 666 617 454 +75 +125 125
UNIT V V V mA V V mW mW mW C C C
1. Mostly dependent on the maximum required Tamb and on the voltage between LN and SLPE (see Figs 6, 7 and 8). 2. Calculated for the maximum ambient temperature specified (Tamb = 75 C) and a maximum junction temperature of 125 C. HANDLING This device meets class 2 ESD test requirements [Human Body Model (HBM)], in accordance with "MIL STD 883C - method 3015". THERMAL CHARACTERISTICS SYMBOL Rth j-a TEA1062; TEA1062A TEA1062M1; TEA1062AM1 TEA1062T; TEA1062AT (note 1) Note 1. Mounted on glass epoxy board 28.5 x 19.1 x 1.5 mm. PARAMETER thermal resistance from junction to ambient in free air 75 81 110 K/W K/W K/W VALUE UNIT
1997 Sep 03
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Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
MLC200
TEA1062; TEA1062A
MLC201
handbook, halfpage
150
I LN (mA)
handbook, halfpage
150
I LN (mA)
130
130
110
(1)
110 (1)
90
(2) (3)
90
(2) (3) (4)
70 (4) 50
70
50
30 2 4 6 8 10 12 V LN V SLPE (V)
(1) (2) (3) (4)
30 2 4 6 8 10 12 V LN V SLPE (V)
(1) Tamb = 45 C; Ptot = 1068 mW. (2) Tamb = 55 C; Ptot = 934 mW. (3) Tamb = 65 C; Ptot = 800 mW. (4) Tamb = 75 C; Ptot = 666 mW.
Tamb = 45 C; Ptot = 988 mW. Tamb = 55 C; Ptot = 864 mW. Tamb = 65 C; Ptot = 741 mW. Tamb = 75 C; Ptot = 617 mW.
Fig.6
TEA1062 and TEA1062A safe operating area.
Fig.7
TEA1062M1 and TEA1062AM1 safe operating area.
MLC202
handbook, halfpage
150
I LN
(mA) 130
110 (1) 90 (2) 70 (3) (4) 50
30 2 4 6 8 10 12 V LN V SLPE (V)
(1) (2) (3) (4)
Tamb = 45 C; Ptot = 727 mW. Tamb = 55 C; Ptot = 636 mW. Tamb = 65 C; Ptot = 545 mW. Tamb = 75 C; Ptot = 454 mW.
Fig.8
TEA1062T and TEA1062AT safe operating area.
1997 Sep 03
10
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
CHARACTERISTICS Iline = 11 to 140 mA; VEE = 0 V; f = 800 Hz; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies LN and VCC (pins 1 and 13) VLN voltage drop over circuit between LN and VEE MIC inputs open-circuit Iline = 1 mA Iline = 4 mA Iline = 15 mA Iline = 100 mA Iline = 140 mA VLN/T VLN variation with temperature voltage drop over circuit between LN and VEE with external resistor RVA supply current supply voltage available for peripheral circuitry TEA1062 VCC supply voltage available for peripheral circuitry TEA1062A Microphone inputs MIC- and MIC+ (pins 6 and 7) Zi input impedance differential single-ended CMRR Gv Gvf GvT common mode rejection ratio voltage gain MIC+ or MIC- to LN gain variation with frequency referenced to 800 Hz gain variation with temperature referenced to 25 C Iline = 15 mA; R7 = 68 k f = 300 and 3400 Hz without R6; Iline = 50 mA; Tamb = -25 and +75 C between MIC- and MIC+ MIC- or MIC+ to VEE - - - 50.5 - - 64 32 82 52.0 0.2 0.2 - - - 53.5 - - k k dB dB dB dB Iline = 15 mA Iline = 15 mA RVA (LN to REG) = 68 k VCC = 2.8 V Iline = 15 mA; MUTE = HIGH Ip = 1.2 mA Ip = 0 mA Iline = 15 mA; MUTE = LOW Ip = 1.2 mA Ip = 0 mA 2.2 - 2.7 3.4 - - V V 2.2 - 2.7 3.4 - - V V - - 3.5 4.5 0.9 - - 1.35 V V mA RVA (REG to SLPE) = 39 k - ICC VCC - - 3.55 4.9 - - 1.6 1.9 4.0 5.7 - -0.3 - - 4.25 6.5 7.5 - V V V V V mV/K
DTMF input (pin 11) |Zi| Gv Gvf GvT input impedance voltage gain from DTMF to LN gain variation with frequency referenced to 800 Hz gain variation with temperature referenced to 25 C Iline = 15 mA; R7 = 68 k f = 300 and 3400 Hz Iline = 50 mA; Tamb = -25 and +75 C - 24.0 - - 20.7 25.5 0.2 0.2 - 27.0 - - k dB dB dB
1997 Sep 03
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Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
SYMBOL Gv PARAMETER CONDITIONS
TEA1062; TEA1062A
MIN. -8
TYP. -
MAX.
UNIT
Gain adjustment inputs GAS1 and GAS2 (pins 2 and 3) transmitting amplifier gain variation by adjustment of R7 between GAS1 and GAS2 0 dB
Sending amplifier output LN (pin 1) VLN(rms) output voltage (RMS value) THD = 10% Iline = 4 mA Iline = 15 mA Vno(rms) noise output voltage (RMS value) Iline = 15 mA; R7 = 68 k; 200 between MIC- and MIC+; psophometrically weighted (P53 curve) - 1.7 - 0.8 2.3 -69 - - - V V dBmp
Receiving amplifier input IR (pin 10) Zi Zo Gv Gvf GvT Vo(rms) input impedance - - Iline = 15 mA; RL = 300 (from pin 9 to pin 4) f = 300 and 3400 Hz without R6; Iline = 50 mA; Tamb = -25 and +75 C THD = 2%; sine wave drive; R4 = 100 k; Iline = 15 mA; Ip = 0 mA RL = 150 RL = 450 Vo(rms) Vno(rms) output voltage (RMS value) noise output voltage (RMS value) THD = 10%; R4 = 100 k; RL = 150 ; Iline = 4 mA Iline = 15 mA; R4 = 100 k; IR open-circuit psophometrically weighted (P53 curve); RL = 300 0.22 0.3 - - 0.33 0.48 15 50 - - - - V V mV V 29.5 - - 21 - - 32.5 - - k dB dB dB
Receiving amplifier output QR (pin 4) output impedance voltage gain from IR to QR gain variation with frequency referenced to 800 Hz gain variation with temperature referenced to 25 C output voltage (RMS value) 4 31 0.2 0.2
Gain adjustment input GAR (pin 5) Gv receiving amplifier gain variation by adjustment of R4 between GAR and QR -11 - 0 dB
Mute input (pin 12) VIH VIL IMUTE HIGH level input voltage LOW level input voltage input current 1.5 - - - - 8 VCC 0.3 15 V V A
1997 Sep 03
12
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
SYMBOL Reduction of gain Gv MIC+ or MIC- to LN TEA1062 TEA1062A Gv voltage gain from DTMF to QR TEA1062 TEA1062A Automatic gain control input AGC (pin 15) Gv controlling the gain from IR to QR and the gain from MIC+, MIC- to LN gain control range IlineH IlineL highest line current for maximum gain lowest line current for minimum gain R6 = 110 k (between AGC and VEE) Iline = 70 mA MUTE = HIGH MUTE = LOW R4 = 100 k; RL = 300 MUTE = HIGH MUTE = LOW PARAMETER CONDITIONS
TEA1062; TEA1062A
MIN.
TYP.
MAX.
UNIT
- - - -
70 70 -17 -17
- - - -
dB dB dB dB
- - -
-5.8 23 61
- - -
dB mA mA
R line
handbook, full pagewidth
I line I SLPE 0.5 mA LN
R1 I CC VCC Ip 0.5 mA C1 peripheral circuits
R exch
TEA1062 TEA1062A
DC AC
Vexch REG STAB I SLPE C3 R5 R9 SLPE
V
EE
MBA357 - 1
Fig.9 Supply arrangement.
1997 Sep 03
13
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
handbook, halfpage
2.4
MSA504
(1) Ip (mA) (2) 1.6
0.8
0 0 1 2 3 V CC (V) 4
The supply possibilities can be increased by setting the voltage drop over the circuit VLN to a higher value by resistor RVA connected between REG and SLPE. VCC > 2.2 V; Iline = 15 mA at VLN = 4 V; R1 = 620 ; R9 = 20 . (1) Ip = 2.1 mA. Is valid when the receiving amplifier is not driven or when MUTE = HIGH (TEA1062), MUTE = LOW (TEA1062A). (2) Ip = 1.7 mA. Is valid when MUTE = LOW (TEA1062), MUTE = HIGH (TEA1062A) and the receiving amplifier is driven; Vo(rms) = 150 mV, RL = 150 .
Fig.10 Typical current Ip available from VCC for peripheral circuitry.
1997 Sep 03
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Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
andbook, full pagewidth
13 7
(1)
MIC
6
V CC MIC
7
MIC
6
MIC
7
6 MIC V EE 9
MIC
MSA505
(a)
(b)
(c)
(a) Magnetic or dynamic microphone. (b) Electret microphone. (c) Piezoelectric microphone. (1) Resistor may be connected to reduce the terminating impedance.
Fig.11 Alternative microphone arrangements.
handbook, full pagewidth
QR
4
QR
4
(1)
QR
4
(2)
V EE
9
V EE 9
VEE
9
MSA506
(a)
(b)
(c)
(a) Dynamic earpiece. (b) Magnetic earpiece. (c) Piezoelectric earpiece. (1) Resistor may be connected to prevent distortion (inductive load). (2) Resistor is required to increase the phase margin (capacitive load).
Fig.12 Alternative receiver arrangements.
1997 Sep 03
15
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
handbook, full pagewidth
0 G v (dB) 2
R6 =
MSA507 - 1
4
78.7 k
110 k
140 k
6
0
20
40
60
80
100
120 140 I line (mA)
R9 = 20 .
Fig.13 Variation of gain as a function of line current with R6 as a parameter.
Table 1
Values of resistor R6 for optimum line-loss compensation at various values of exchange supply voltage (Vexch) and exchange feeding bridge resistance (Rexch); R9 = 20 . R6 (k)
Vexch (V) 36 48 60
Rexch = 400 100 140 -
Rexch = 600 78.7 110 -
Rexch = 800 - 93.1 120
Rexch = 1000 - 82 102
1997 Sep 03
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Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
R1
handbook, full pagewidth
I line 1 LN 100 F RL 600 R4 100 k C4 100 pF Vo
13 10 7 Vi 6 11 12 IR MIC MIC DTMF MUTE VCC
620
QR
4
100 F C1
TEA1062
GAR
5 2
C7 1 nF GAS1 C8 1 nF C6 100 pF 10 to 140 mA
10 F Vi GAS2 V EE 9 C3 4.7 F REG AGC STAB SLPE 14 15 8 16 R6 R5 3.6 k R9 20 3
R7 68 k
MSA508
Voltage gain is defined as Gv = 20 log Vo/Vi. For measuring gain from MIC+ and MIC- the MUTE input should be LOW or open-circuit. For measuring the DTMF input, the MUTE input should be HIGH. Inputs not being tested should be open-circuit.
Fig.14 Test circuit for defining TEA1062 voltage gain of MIC+, MIC- and DTMF inputs.
1997 Sep 03
17
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
R1
handbook, full pagewidth
I line 1 LN 100 F RL 600 R4 100 k C4 100 pF Vo
13 10 7 Vi 6 11 12 10 F Vi IR MIC VCC
620
QR MIC DTMF MUTE
4
100 F C1
TEA1062A
GAR
5 2
C7 1 nF GAS1 C8 1 nF C6 100 pF 10 to 140 mA
GAS2 V EE 9 C3 4.7 F REG 14 AGC 15 R6 STAB SLPE 16 8 R5 3.6 k R9 20
3
R7 68 k
MBA355
Voltage gain is defined as Gv = 20 log Vo/Vi. For measuring gain from MIC+ and MIC- the MUTE input should be HIGH. For measuring the DTMF input, the MUTE input should be LOW or open-circuit. Inputs not being tested should be open-circuit.
Fig.15 Test circuit for defining TEA1062A voltage gain of MIC+, MIC- and DTMF inputs.
1997 Sep 03
18
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
R1
handbook, full pagewidth
I line 1 LN 4 C2 ZL Vo C4 100 pF 100 F 600
13 10 7 Vi 10 F 6 11 C1 100 F 12 MUTE IR MIC MIC DTMF VCC
620
QR
TEA1062
GAR GAS1
5 2
R4 100 k
C7 1 nF 10 to 140 mA R7 C8 1 nF C6 100 pF
GAS2 V EE 9 C3 4.7 F REG 14 AGC 15 R6 STAB SLPE 8 R5 3.6 k 16 R9 20
3
MSA509
Voltage gain is defined as Gv = 20 log Vo/Vi.
Fig.16 Test circuit for defining TEA1062 voltage gain of the receiving amplifier.
R1
handbook, full pagewidth
I line 1 LN 4 C2 ZL Vo C4 100 pF 100 F 600
13 10 7 Vi 10 F 6 11 C1 100 F 12 MUTE IR MIC MIC DTMF VCC
620
QR
TEA1062A
GAR GAS1
5 2
R4 100 k
C7 1 nF 10 to 140 mA R7 C8 1 nF C6 100 pF
GAS2 V EE 9 C3 4.7 F REG AGC STAB SLPE 14 15 8 16 R6 R5 3.6 k R9 20
3
MBA356
Voltage gain is defined as Gv = 20 log Vo/Vi.
Fig.17 Test circuit for defining TEA1062A voltage gain of the receiving amplifier.
1997 Sep 03
19
TEA1062; TEA1062A
Product specification
Fig.18 Typical application of TEA1062A, with piezoelectric earpiece and DTMF dialling.
handbook, full pagewidth
1997 Sep 03
R1 R2 130 k C5 10 IR DTMF QR 11 100 nF LN VCC C1 100 F C2 1 620 13 4 C4 100 pF 5 GAR
(1)
Philips Semiconductors
APPLICATION INFORMATION
R10 13 BAS11 (2x)
BZX79 C12
telephone line
BZW14 (2x) C7 1 nF 7 MIC MIC REG 14 AGC 15 STAB 8 VEE 9 SLPE GAS1 GAS2 16 2 3 C6 R7 100 pF R VA(R 16 - 14 ) C8 1 nF C3 4.7 F 6 MUTE 12
Low voltage transmission circuits with dialler interface
R4 R3 3.92 k
TEA1062A
from dial and control circuits
20
R8 390 Z bal R9 20 R6 R5 3.6 k
MBA358 - 1
The diode bridge, the Zener diode and R10 limit the current into, and the voltage across, the circuit during line transients. A different protection arrangement is required for pulse dialling or register recall. The DC line voltage can be set to a higher value by the resistor RVA (REG to SLPE). Further application information can be found in our publication "Applications Handbook for Wired telecom systems, IC03b", order number 9397 750 00811. (1) Pin 12 is active HIGH (MUTE) for TEA1062.
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
R1
handbook, full pagewidth
620 LN VCC DTMF MUTE VDD TONE M1 PCD3310 DP/FLO
cradle contact
TEA1062
VEE telephone line BSN254A
VSS
MLC203
(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310. The dashed line shows an optional flash (register recall by timed loop break).
Fig.19 Typical simplified application of the TEA1062.
handbook, full pagewidth
R1 620 LN VCC DTMF MUTE VDD TONE M1 PCD3310T DP/FLO
cradle contact
TEA1062A
VEE telephone line BSN254A
VSS
MLC204
(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310T. The dashed line shows an optional flash (register recall by timed loop break).
Fig.20 Typical simplified application of the TEA1062A.
1997 Sep 03
21
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body
TEA1062; TEA1062A
SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-02 95-01-19
1997 Sep 03
22
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.030
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1997 Sep 03
23
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-9
seating plane
D
ME
A2
A
L
A1
Z
e
b1
wM
c (e1)
b 16 9
b2
MH
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) UNIT mm inches A max. 4.32 0.17 A1 min. 0.38 0.015 A2 max. 3.56 0.14 b 1.65 1.40 0.065 0.055 b1 0.51 0.41 0.020 0.016 b2 1.14 0.76 0.045 0.030 c 0.36 0.20 0.014 0.008 D (1) 19.30 18.80 0.76 0.74 E (1) 6.45 6.24 0.254 0.246 e 2.54 0.10 e1 7.62 0.30 L 3.81 2.92 0.150 0.115 ME 8.23 7.62 0.324 0.300 MH 9.40 8.38 0.37 0.33 w 0.254 0.01 Z (1) max. 0.76 0.030
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT38-9 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-07-24
1997 Sep 03
24
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
TEA1062; TEA1062A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1997 Sep 03
25
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s. Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications.
TEA1062; TEA1062A
BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
1997 Sep 03
26
Philips Semiconductors
Product specification
Low voltage transmission circuits with dialler interface
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TEA1062; TEA1062A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Sep 03
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417027/1200/05/pp28
Date of release: 1997 Sep 03
Document order number:
9397 750 02819

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